AES PLBProject repository for my AES PLB core. This core is designed to be used as a PLB peripheral using the Xilinx Platform Studio.

All associated files (user logic and drivers) are (or will be shortly) in the SVN repository.

The design of this core is to be as easy to use as possible in the wrapper between PLB interface and the AES IP.

NOTE: This is a work in progress still, and is not complete. Expect files up by the end of this week (3/19/20008)

NEWS5/2/2008 The original IP core I choose relied upon delays for its pre-synthesis simulation to appear to match FIPS197. Obviously, this crashed and burned very badly upon implementation and the discovery that the post synthesis implementation was b0rked. I've choosen a new core and was able to drop it into my existing design with no problems, but am having trouble interfacing my IP into the IPIC interface...

3/19/2008 SVN is difficult to setup for a whole XPS project directory, so I'm probably only going to be hosting the drivers (.c and .h files) and the pcore (user_logic.v & associated AES files) information. There will be the documents needed to successfully import this peripheral into a XPS design.

I will be hosting test applications.